Overview

Digital signal processing (DSP) within FPGA makes it possible to tailor the implementation to match system requirements. For multiple-channel or high-speed system, FPGA has the parallelism capability to maximize performance while in lower-rate system the implementation may have more serial in nature. Therefore, the DSP engineer can tailor the implementation to suit the algorithm and system requirements rather than compromising the desired ideal design to conform to the limitations of conventional digital signal processors.

System generator for DSP is a model-based DSP design tool in the Vivado Design Suite that enables you to use the MathWorks model-based Simulink design environment for FPGA design. It is useful for algorithm exploration, design prototyping, and model analysis. Often System Generator is used to implement a portion of a larger design, especially implementation of data paths and controls. Previous experience with Xilinx FPGA devices or RTL design methodologies is not required when using System Generator.

For DSP Engineer, System Generator extends Simulink to enable hardware design by providing high-level abstraction that can be automatically compiled into and FPGA. For Hardware Engineer, System Generator does not replace hardware description language (HDL)-based design but does makes it possible to focus the attention only on the critical paths. Therefore, DSP Engineer and Hardware Engineer can make full use of this tool to design and to verify the design onto the hardware.