![[Free Training ] Hardware Design Using HDL Library on Vitis Model Composer (1 Day) [Free Training ] Hardware Design Using HDL Library on Vitis Model Composer (1 Day)](https://event.techsource-asia.com/hs-fs/hubfs/%5BFree%20Training%20%5D%20Hardware%20Design%20Using%20HDL%20Library%20on%20Vitis%20Model%20Composer%20(1%20Day).png?width=1920&height=1080&name=%5BFree%20Training%20%5D%20Hardware%20Design%20Using%20HDL%20Library%20on%20Vitis%20Model%20Composer%20(1%20Day).png)
Model Composer is a system-level modeling tool that facilitates FPGA hardware design. It extends Simulink® in many ways to provide a modeling environment that is well-suited to hardware design. The tool provides high-level abstractions that are automatically compiled into an FPGA at the push of a button. The tool also provides access to underlying FPGA resources through low-level abstractions, allowing the construction of highly efficient FPGA designs.
In this workshop, you will learn about the Model-Based Design workflow using Model Composer, how to set up the Simulink model using blocks from HDL library and do automatic code generation, and how to import a Model Composer HDL design into a bigger system.
All rights reserved. Copyright © 2025 TechSource Systems and Ascendas Systems Group