Live Webinar

How to Generate Error-free Synthesizable RTL to Target Any FPGA, ASIC, SoC Device?
11.05.2020 | 15:00-16:00(GMT+8)
Online via Webex

20% off for Virtual Classroom Training until June 23 in collaboration with Xilinx

FPGA Wave

About The Event

Domain experts and hardware engineers use MATLAB and Simulink to develop prototype and production applications for deployment on FPGA, ASIC, and SoC devices.

Simulink provides an environment for system architects and hardware designers to exchange information, ideas and designs. Add-on toolbox such as HDL Coder enables users to generate optimized, readable, and traceable VHDL or Verilog for implementation in digital logic design. The environment also offers the ability to verify your algorithm in an HDL Simulator or on an FPGA or SoC device connected to your MATLAB or Simulink test bench.
FPGA Image1

This webinar covers topics that allow automation of FPGA, ASICs and SoC applications workflow from algorithm development to hardware design and verification.

Topics Include: 

  • Use Simulink to model and simulate algorithm at high level abstraction
  • Option to convert the Simulink model to fixed-point for any target device
  • Generate readable and traceable HDL code
  • Verify the algorithm in an HDL Simulator

The Speaker

marta
Dr Marta Patricia Tjoa
Trainer and Senior Training Consultant

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