Event Details

Date: 9, 10 & 11 July 2025

Time: 5:30 pm - 6:30 pm (GMT+8)

Location: Online

Join us for an engaging three-part webinar series on "Semiconductor Design and Verification," where we delve into the critical aspects of analog and mixed-signal (AMS) component verification in semiconductor design. This series is tailored for engineers and professionals seeking to enhance their understanding and capabilities in AMS design and verification using MathWorks tools.

Why Attend?

Explore 3 critical pillars of decarbonization where innovation is driving impact:

•  Session 1 - Early Verification of Analog & Mixed Signal Components for Semiconductor Design  
  • Discover how MathWorks tools can be leveraged to model and simulate mixed-signal systems at various abstraction levels
    

• Session 2 - Integrated EDA Workflows for AMS IC Design and Verification 
  • Explore AMS IC design and verification workflows, focusing on the DPIC workflow for mixed-mode simulation. We will also cover netlist import and co-simulation with other EDA vendors
    

• Session 3 - Modeling and Simulation of High-Speed Links & Interconnects 
  • Streamline your system design and analysis process from initial SerDes system floor planning to detailed system design and robust signal integrity analysis.
  • Presentation from Ranjan Sahoo of NXP on how NXP Semiconductors Streamlines High-Speed Interface Design with SERDES Toolbox

Who Should Join?

This webinar series is ideal for semiconductor engineers, design verification specialists, and system architects who are keen to enhance their skills in AMS design and verification. Whether you are a seasoned professional looking to stay ahead of the curve or a newcomer eager to learn cutting-edge techniques, this series offers valuable insights and practical knowledge.

Don’t miss this opportunity to learn from industry experts and transform your AMS design approach!

About the Presenters

Ranjan Sahoo | Technical Director, SCE | NXP Semiconductors

Ranjan K Sahoo is a seasoned technology leader with over 22 years of experience in the semiconductor industry, having worked with renowned organizations such as Cypress, Intel, and NXP. He currently serves as a Technical Director, SCE, focusing on high-speed interfaces including USB 3.2 and DisplayPort 1.4.

He holds an M.Tech degree in VLSI Design from IIT Madras and brings deep technical expertise in high-speed circuit and system design, analog circuit design, and digitally assisted system performance optimization.

Jahnavi Dhulipala | Senior Application Engineer | MathWorks

Jahnavi Dhulipala is a senior application engineer at MathWorks and is based in Bangalore. She specializes in RF, analog, and mixed-signal component and system design and works with tier-1 semiconductor and electronics companies to help support their adoption and success with top-down and model-driven system design and verification workflows.