What you'll learn :
This comprehensive course is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall Verilog proficiency and enhance your FPGA optimization. This course covers Verilog 1995 and 2001. You will gain valuable hands-on experience. Incoming students with little or no Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.
Essentials of FPGA Design module is specially designed for designers new to FPGAs design or programmable logic. Build an effective FPGA design using synchronous design techniques, instantiate appropriate device resources, use proper HDL coding techniques, make good pin assignments, set basic XDC timing constraints, and use the Vivado® Design Suite to build, synthesize, implement, and download a design.
Hands-on Project on the last day allows you to test your knowledge and apply your skills immediately. No documentation, no labs instructions, you will face the real challenge to do a full FPGA design flow project with the guidance of our instructor.
Complete the form to get a course brochure and consult with our training consultant.
VHDL and FPGA Design Expert
This is a comprehensive training package that comprises of 2 course modules: Designing with VHDL and Designing FPGAs Using the Vivado Design Suite 1.Based on Xilinx industry standard, this 6-day training package can be considered as the minimum training requirement for project readiness.
Advanced Timing Closure Techniques for the Vivado Design Suite
Achieving repeatable and reliable timing is the designer’s ultimate goal. Learn advanced Vivado timing closure techniques to improve FPGA design speed and reliability.
Zynq UltraScale+ MPSoC for the System Architect
Learn everything you need to kickstart a MPSoC project in 2-3 days from our experienced trainer who has hands-on skills on the project.
Accelerating Applications with the Vitis Unified Software Environment
Learn how to develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™ unified software environment targeting both data center (DC) and embedded applications.