This is a comprehensive training package that comprises of 2 course modules: Designing with VHDL and Designing FPGAs Using the Vivado Design Suite 1.Based on Xilinx industry standard, this 6-day training package can be considered as the minimum training requirement for project readiness.
Designing with VHDL (3-day) provides a thorough introduction to the VHDL language. The emphasis is on writing efficient hardware designs, performing high-level HDL simulations, employing structural, register transfer level (RTL), and behavioral coding styles, targeting Xilinx devices specifically and FPGA devices in general, utilizing best coding practices.
Essentials of FPGA Design (2-day) is specially designed for designers new to FPGAs design or programmable logic. Build an effective FPGA design using synchronous design techniques, instantiate appropriate device resources, use proper HDL coding techniques, make good pin assignments, set basic XDC timing constraints, and use the Vivado® Design Suite to build, synthesize, implement, and download a design.
Hands-on Project (1-day) on the last day allows you to test your knowledge and apply your skills immediately. No documentation, no labs instructions, you will face the real challenge to do a full FPGA design flow project with the guidance of our instructor.
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Verilog and FPGA Design Expert
This is a comprehensive training package that comprises of 2 course modules: Designing with Verilog and Designing FPGAs Using the Vivado Design Suite 1. Based on Xilinx industry standard, this 6-day training package can be considered as the minimum training requirement for project readiness.
Advanced Timing Closure Techniques for the Vivado Design Suite
Achieving repeatable and reliable timing is the designer’s ultimate goal. Learn advanced Vivado timing closure techniques to improve FPGA design speed and reliability.
Zynq UltraScale+ MPSoC for the System Architect
Learn everything you need to kickstart a MPSoC project in 2-3 days from our experienced trainer who has hands-on skills on the project.
Accelerating Applications with the Vitis Unified Software Environment
Learn how to develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™ unified software environment targeting both data center (DC) and embedded applications.